Application-specific instruction set processor

An application-specific instruction set processor (ASIP) is a component used in system on a chip design. The instruction set architecture of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose central processing unit (CPU) and the performance of an application-specific integrated circuit (ASIC).

Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: static logic which defines a minimum ISA (instruction-set architecture) and configurable logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to a field-programmable gate array (FPGA) or during the chip synthesis. ASIPs have two ways of generating code: either through a retargetable code generator or through a retargetable compiler generator. The retargetable code generator uses the application, ISA, and Architecture Template to create the code generator for the object code. The retargetable compiler generator uses only the ISA and Architecture Template as the basis for creating the compiler. The application code will then be used by the compiler to create the object code.[1]

ASIPs can be used as an alternative of hardware accelerators for baseband signal processing[2] or video coding.[3] Traditional hardware accelerators for these applications suffer from inflexibility. It is very difficult to reuse the hardware datapath with handwritten finite-state machines (FSM). The retargetable compilers of ASIPs help the designer to update the program and reuse the datapath. Typically, the ASIP design is more or less dependent on the tool flow because designing a processor from scratch can be very complicated. One approach is to describe the processor using a high level language and then to automatically generate the ASIP's software toolset.[4]

  1. ^ Jain, M.K.; Balakrishnan, M.; Kumar, A. (2001). "ASIP design methodologies: Survey and issues". VLSI Design 2001. Fourteenth International Conference on VLSI Design. Bangalore, India: IEEE Comput. Soc. pp. 76–81. doi:10.1109/ICVD.2001.902643. ISBN 978-0-7695-0831-3. S2CID 14053636.
  2. ^ Shahabuddin, Shahriar et al., "Design of a transport triggered vector processor for turbo decoding", Springer Journal of Analog Integrated Circuits and Signal Processing, March 2014.
  3. ^ Hautala, Ilkka, et al. "Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering" in IEEE Transactions on Circuits and Systems for Video Technology, November 2014
  4. ^ Masarík, UML in design of ASIP, IFAC Proceedings Volumes 39(17):209-214, September 2006