 | This article has multiple issues. Please help improve it or discuss these issues on the talk page. (Learn how and when to remove these messages)
|
Boundary scan is a method for testing interconnects (wire lines) on printed circuit boards or sub-blocks inside an integrated circuit. Boundary scan is also widely used as a debugging method to watch integrated circuit pin states, measure voltage, or analyze sub-blocks inside an integrated circuit.
The Joint Test Action Group (JTAG) developed a specification for boundary scan testing that was standardized in 1990 as the IEEE Std. 1149.1-1990. In 1994, a supplement that contains a description of the Boundary Scan Description Language (BSDL) was added which describes the boundary-scan logic content of IEEE Std 1149.1 compliant devices. Since then, this standard has been adopted by electronic device companies all over the world. Boundary scan is now mostly synonymous with JTAG.[1][2]
- ^ IEEE Std 1149.1 (JTAG) Testability Primer Chapter 3 covers boundary scan with JTAG, and other chapters are also informative.
- ^ Frenzel, Louis E. (September 11, 2008). "The Embedded Plan For JTAG Boundary Scan". Electronic Design. Archived from the original on 2008-12-01. presents an overview, circa 2008.