In integrated circuit design, dynamic logic (or sometimes clocked logic) is a design methodology in combinational logic circuits, particularly those implemented in metal–oxide–semiconductor (MOS) technology. It is distinguished from the so-called static logic by exploiting temporary storage of information in stray and gate capacitances.[1] It was popular in the 1970s and has seen a recent resurgence in the design of high-speed digital electronics[citation needed], particularly central processing units (CPUs). Dynamic logic circuits are usually faster than static counterparts and require less surface area, but are more difficult to design. Dynamic logic has a higher average rate of voltage transitions than static logic,[2] but the capacitive loads being transitioned are smaller[3] so the overall power consumption of dynamic logic may be higher or lower depending on various tradeoffs. When referring to a particular logic family, the dynamic adjective usually suffices to distinguish the design methodology, e.g. dynamic CMOS[4] or dynamic SOI design.[2]
Besides its use of dynamic state storage via voltages on capacitances, dynamic logic is distinguished from so-called static logic in that dynamic logic uses a clock signal in its implementation of combinational logic. The usual use of a clock signal is to synchronize transitions in sequential logic circuits. For most implementations of combinational logic, a clock signal is not even needed. The static/dynamic terminology used to refer to combinatorial circuits is related to the use of the same adjectives used to distinguish memory devices, e.g. static RAM from dynamic RAM, in that dynamic RAM stores state dynamically as voltages on capacitances, which must be periodically refreshed. But there are also differences in usage; the clock can be stopped in the appropriate phase in a system with dynamic logic and static storage.[5]