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| Character | Value |
|---|---|
'U' |
uninitialized |
'X' |
strong drive, unknown logic value |
'0' |
strong drive, logic zero |
'1' |
strong drive, logic one |
'Z' |
high impedance |
'W' |
weak drive, unknown logic value |
'L' |
weak drive, logic zero |
'H' |
weak drive, logic one |
'-' |
don't care |
The IEEE 1164 standard (Multivalue Logic System for VHDL Model Interoperability) is a technical standard published by the IEEE in 1993. It describes the definitions of logic values to be used in electronic design automation, for the VHDL hardware description language.[2] It was sponsored by the Design Automation Standards Committee of the Institute of Electrical and Electronics Engineers (IEEE). The standardization effort was based on the donation of the Synopsys MVL-9 type declaration.
The primary data type std_ulogic (standard unresolved logic) consists of nine character literals (see table on the right).[1] This system promoted a useful set of logic values that typical CMOS logic designs could implement in the vast majority of modeling situations, including:
'Z'literal to make tri-state buffer logic easy'H'and'L'weak drives to permit wired-AND and wired-OR logic.'U'for default value for all object declarations so that during simulations uninitialized values are easily detectable and thus easily corrected if necessary.
In VHDL, the hardware designer makes the declarations visible via the following library and use statements:
library IEEE;
use IEEE.std_logic_1164.all;
- ^ a b "VHDL and Logic Synthesis". Retrieved 22 January 2010.
- ^ "IEEE 1164-1993 – IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164)". IEEE. Retrieved 25 September 2018.