 PMOS SC/MP die (ISP-8A/500) | |
| General information | |
|---|---|
| Launched | April 1976 |
| Common manufacturer | |
| Performance | |
| Max. CPU clock rate | 1 MHz to 4 MHz |
| Data width | 8 bits |
| Address width | 16 bits |
| Physical specifications | |
| Package |
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National Semiconductor's SC/MP (pronounced scamp) for Simple Cost-effective Micro Processor, is an early 8-bit microprocessor which became available in April 1976. It was designed to allow systems to be implemented with the minimum number of additional support chips. SC/MP included a daisy-chained control pin that allowed up to three SC/MP's share a single main memory to produce a multiprocessor system, or to act as controllers in a system with another main central processing unit (CPU). Three versions were released over its lifetime, SCMP-1 through 3, the latter two also known as INS8060 and INS8070.
To lower cost, the system used a bit-serial arithmetic logic unit (ALU) and was thus significantly slower than contemporary designs like the Intel 8080 or MOS 6502 which had parallel ALUs. Another oddity was that the program counter could only access the lower 12-bits of the 16-bit address, and the upper 4-bits had to be set using special instructions. The result was that instructions accessed main memory as sixteen 4 kB "pages" and reaching memory outside those pages required multiple instructions.[a]
The combination of slow speed and paged memory limited its attractiveness outside the embedded markets it was aimed at, and in this market it competed against the Fairchild F8 which had a number of useful additional features. The system saw relatively little use.
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