P6 (microarchitecture)

P6
Die shot of Deschutes core
General information
LaunchedNovember 1, 1995; 29 years ago (November 1, 1995)
Performance
Max. CPU clock rate150[1] MHz to 1.40 GHz
FSB speeds66 MHz to 133 MHz
Cache
L1 cachePentium Pro: 16 KB (8 KB I cache + 8 KB D cache)
Pentium II/III: 32 KB (16 KB I cache + 16 KB D cache)
L2 cache128 KB to 512 KB
256 KB to 2048 KB (Xeon)
Architecture and classification
MicroarchitectureP6
Instruction setx86-16, IA-32
Extensions
  • MMX (Pentium II/III/M)
    SSE (Pentium III/M)
    SSE2 (Pentium M)
Physical specifications
Transistors
Cores
  • 1
Sockets
Products, models, variants
Models
  • Pentium Pro Series
  • Celeron II Series
  • Pentium II Series
  • Pentium II Xeon Series
  • Celeron III Series
  • Pentium III Series
  • Pentium III Xeon Series
History
PredecessorP5
SuccessorNetBurst
Support status
Unsupported

The P6 microarchitecture is the sixth-generation Intel x86 microarchitecture, implemented by the Pentium Pro microprocessor that was introduced in November 1995. It is frequently referred to as i686.[2] It was planned to be succeeded by the NetBurst microarchitecture used by the Pentium 4 in 2000, but was revived for the Pentium M line of microprocessors. The successor to the Pentium M variant of the P6 microarchitecture is the Core microarchitecture which in turn is also derived from P6.

P6 was used within Intel's mainstream offerings from the Pentium Pro to Pentium III, and was widely known for low power consumption, excellent integer performance, and relatively high instructions per cycle (IPC).

  1. ^ "Pentium® Pro Processor at 150 MHz, 166 MHz, 180 MHz and 200 MHz" (PDF). Intel Corporation. November 1995. p. 1. Archived from the original (PDF) on April 12, 2016.
  2. ^ Hutchings, Ben (September 28, 2015). "Defaulting to i686 for the Debian i386 architecture". debian-devel (Mailing list).