General information | |
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Launched | 2010 |
Designed by | IBM |
Performance | |
Max. CPU clock rate | 2.4 GHz to 4.25 GHz |
Cache | |
L1 cache | 32+32 KB/core |
L2 cache | 256 KB/core |
L3 cache | 4 MB/core |
Architecture and classification | |
Technology node | 45 nm |
Instruction set | Power ISA (Power ISA v.2.06) |
Physical specifications | |
Cores |
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History | |
Predecessor | POWER6 |
Successor | POWER8 |
POWER, PowerPC, and Power ISA architectures |
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NXP (formerly Freescale and Motorola) |
IBM |
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IBM/Nintendo |
Other |
Related links |
Cancelled in gray, historic in italic |
POWER7 is a family of superscalar multi-core microprocessors based on the Power ISA 2.06 instruction set architecture released in 2010 that succeeded the POWER6 and POWER6+. POWER7 was developed by IBM at several sites including IBM's Rochester, MN; Austin, TX; Essex Junction, VT; T. J. Watson Research Center, NY; Bromont, QC[1] and IBM Deutschland Research & Development GmbH, Böblingen, Germany laboratories. IBM announced servers based on POWER7 on 8 February 2010.[2][3]