The completed design is housed in 10 19-inch racks, with each rack holding over 100,000 cores.[13] The cards holding the chips are held in 5 blade enclosures, and each core emulates 1,000 neurons.[13] In total, the goal is to simulate the behaviour of aggregates of up to a billion neurons in real time.[14] This machine requires about 100 kW from a 240 V supply and an air-conditioned environment.[15]
On 14 October 2018 the HBP announced that the million core milestone had been achieved.[18][19]
On 24 September 2019 HBP announced that an 8 million euro grant, that will fund construction of the second generation machine, (called SpiNNcloud) has been given to TU Dresden.[20]
^Yan, Yexin; Kappel, David; Neumarker, Felix; Partzsch, Johannes; Vogginger, Bernhard; Hoppner, Sebastian; Furber, Steve; Maass, Wolfgang; Legenstein, Robert; Mayr, Christian (2019). "Efficient Reward-Based Structural Plasticity on a SpiNNaker 2 Prototype". IEEE Transactions on Biomedical Circuits and Systems. 13 (3): 579–591. arXiv:1903.08500. Bibcode:2019arXiv190308500Y. doi:10.1109/TBCAS.2019.2906401. ISSN1932-4545. PMID30932847. S2CID84186422.
^Xin Jin; Furber, S. B.; Woods, J. V. (2008). "Efficient modelling of spiking neural networks on a scalable chip multiprocessor". 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence). pp. 2812–2819. doi:10.1109/IJCNN.2008.4634194. ISBN978-1-4244-1820-6. S2CID2103654.
^Plana, L. A.; Furber, S. B.; Temple, S.; Khan, M.; Shi, Y.; Wu, J.; Yang, S. (2007). "A GALS Infrastructure for a Massively Parallel Multiprocessor". IEEE Design & Test of Computers. 24 (5): 454. doi:10.1109/MDT.2007.149. S2CID16758888. A description of the Globally Asynchronous, Locally Synchronous (GALS) nature of SpiNNaker, with an overview of the asynchronous communications hardware designed to transmit neural 'spikes' between processors.
^Navaridas, J.; Luján, M.; Miguel-Alonso, J.; Plana, L. A.; Furber, S. (2009). "Understanding the interconnection network of SpiNNaker". Proceedings of the 23rd international conference on Conference on Supercomputing - ICS '09. p. 286. CiteSeerX10.1.1.634.9481. doi:10.1145/1542275.1542317. ISBN9781605584980. S2CID3710084. Modelling and analysis of the SpiNNaker interconnect in a million-core machine, showing the suitability of the packet-switched network for large-scale spiking neural network simulation.
^Rast, A.; Galluppi, F.; Davies, S.; Plana, L.; Patterson, C.; Sharp, T.; Lester, D.; Furber, S. (2011). "Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware". Neural Networks. 24 (9): 961–978. doi:10.1016/j.neunet.2011.06.014. PMID21778034. A demonstration of SpiNNaker's ability to simulate different neural models (simultaneously, if necessary) in contrast to other neuromorphic hardware.
^Sharp, T.; Galluppi, F.; Rast, A.; Furber, S. (2012). "Power-efficient simulation of detailed cortical microcircuits on SpiNNaker". Journal of Neuroscience Methods. 210 (1): 110–118. doi:10.1016/j.jneumeth.2012.03.001. PMID22465805. S2CID19083072. Four-chip, real-time simulation of a four-million-synapse cortical circuit, showing the extreme energy efficiency of the SpiNNaker architecture