| Paradigm | Structured (design) Object-oriented (verification) |
|---|---|
| Designed by | Synopsys, later IEEE |
| First appeared | 2002 |
| Stable release | IEEE 1800-2023
/ December 16, 2023 |
| Typing discipline | Static, weak |
| Filename extensions | .sv, .svh |
| Influenced by | |
| Design: Verilog, VHDL, C++, Verification: OpenVera, Java | |
SystemVerilog, standardized as IEEE 1800, is a hardware description and hardware verification language used to model, design, simulate, test and implement electronic systems. SystemVerilog is based on Verilog and some extensions, and since 2008, Verilog is now part of the same IEEE standard. It is commonly used in the semiconductor and electronic design industry as an evolution of Verilog.