General information | |
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Launched | 2006 |
Designed by | Intel Tera-Scale Computing Research Program |
Performance | |
Max. CPU clock rate | 5.67 GHz |
Data width | 38-bit |
Architecture and classification | |
Instruction set | 96-bit VLIW |
Physical specifications | |
Transistors |
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Cores |
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Socket |
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History | |
Successor | Xeon Phi |
Intel Teraflops Research Chip (codenamed Polaris) is a research manycore processor containing 80 cores, using a network-on-chip architecture, developed by Intel's Tera-Scale Computing Research Program.[1] It was manufactured using a 65 nm CMOS process with eight layers of copper interconnect and contains 100 million transistors on a 275 mm2 die.[2][3][4] Its design goal was to demonstrate a modular architecture capable of a sustained performance of 1.0 TFLOPS while dissipating less than 100 W.[3] Research from the project was later incorporated into Xeon Phi. The technical lead of the project was Sriram R. Vangal.[4]
The processor was initially presented at the Intel Developer Forum on September 26, 2006[5] and officially announced on February 11, 2007.[6] A working chip was presented at the 2007 IEEE International Solid-State Circuits Conference, alongside technical specifications.[2]
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