Tunnel field-effect transistor

The tunnel field-effect transistor (TFET) is an experimental type of transistor. Even though its structure is very similar to a metal–oxide–semiconductor field-effect transistor (MOSFET), the fundamental switching mechanism differs, making this device a promising candidate for low power electronics. TFETs switch by modulating quantum tunneling through a barrier instead of modulating thermionic emission over a barrier as in traditional MOSFETs. Because of this, TFETs are not limited by the thermal Maxwell–Boltzmann tail of carriers, which limits MOSFET drain current subthreshold swing to about 60 mV/decade of current at room temperature.

TFET studies can be traced back to Stuetzer who in 1952 published first investigations of a transistor containing the basic elements of the TFET, a gated p-n junction. The reported surface conductivity control was, however, not related to tunneling.^[1] The first TFET was reported in 1965.^[2] Joerg Appenzeller and his colleagues at IBM were the first to demonstrate that current swings below the MOSFET’s 60-mV-per-decade limit were possible. In 2004, they reported they had created a tunnel transistor with a carbon nanotube channel and a subthreshold swing of just 40 mV per decade.^[3] Theoretical work has indicated that significant power savings can be obtained by using low-voltage TFETs in place of MOSFETs in logic circuits.^[4]

In classical MOSFET devices, the 60 mV/decade is a fundamental limit to power scaling. The ratio between on-current and the off-current (especially the subthreshold leakage — one major contributor of power consumption) is given by the ratio between the threshold voltage and the subthreshold slope, e.g.:

${\displaystyle n=60\,\,\mathrm {mV/decade} ;\,\,\,V_{\rm {th}}=300\,\,\mathrm {mV} \,\,\rightarrow \,\,I_{\rm {on}}/I_{\rm {off}}=V_{\rm {th}}/n=5\,\,\mathrm {decades} =100\,000}$

The transistor speed is proportional to the on-current: The higher the on-current, the faster a transistor will be able to charge its fan-out (consecutive capacitive load). For a given transistor speed and a maximum acceptable subthreshold leakage, the subthreshold slope thus defines a certain minimal threshold voltage. Reducing the threshold voltage is an essential part for the idea of constant field scaling. Since 2003, the major technology developers got almost stuck in threshold voltage scaling and thus could also not scale supply voltage (which due to technical reasons has to be at least 3 times the threshold voltage for high performance devices). As a consequence, the processor speed did not develop as fast as before 2003 (see Beyond CMOS). The advent of a mass-producible TFET device with a slope far below 60 mV/decade will enable the industry to continue the scaling trends from the 1990s, where processor frequency doubled each 3 years.