Semiconductor device fabrication |
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MOSFET scaling (process nodes) |
Future
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The "14 nanometer process" refers to a marketing term for the MOSFET technology node that is the successor to the "22 nm" (or "20 nm") node. The "14 nm" was so named by the International Technology Roadmap for Semiconductors (ITRS). Until about 2011, the node following "22 nm" was expected to be "16 nm". All "14 nm" nodes use FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology that is a non-planar evolution of planar silicon CMOS technology.
Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit;[1] neither gate length, metal pitch or gate pitch on a "14nm" device is fourteen nanometers.[2][3][4] For example, TSMC and Samsung's "10 nm" processes are somewhere between Intel's "14 nm" and "10 nm" processes in transistor density, and TSMC's "7 nm" processes are dimensionally similar to Intel's "10 nm" process.[5]
Samsung Electronics taped out a "14 nm" chip in 2014, before manufacturing "10 nm class" NAND flash chips in 2013.[dubious – discuss][clarification needed] The same year, SK Hynix began mass-production of "16 nm" NAND flash, and TSMC began "16 nm" FinFET production. The following year, Intel began shipping "14 nm" scale devices to consumers.[needs update]