2.5D integrated circuit

A 2.5D integrated circuit (2.5D IC) is an advanced packaging technique[1] that combines multiple integrated circuit dies in a single package[2] without stacking them into a three-dimensional integrated circuit (3D-IC) with through-silicon vias (TSVs).[3] The term "2.5D" originated when 3D-ICs with TSVs were quite new and still very difficult. Chip designers realized that many of the advantages of 3D integration could be approximated by placing bare dies side by side on an interposer instead of stacking them vertically. If the pitch is very fine and the interconnect very short, the assembly can be packaged as a single component with better size, weight, and power characteristics than a comparable 2D circuit board assembly. This half-way 3D integration was facetiously named "2.5D" and the name stuck.[3] Since then, 2.5D has proven to be far more than just "half-way to 3D."[4] Some benefits:

  • An interposer can support heterogeneous integration – that is, dies of different pitch, size, material, and process node.[5]
  • Placing dies side by side instead of stacking them reduces heat buildup.[6]
  • Upgrading or modifying a 2.5D assembly is as easy as swapping in a new component and revamping the interposer to suit; much faster and simpler than reworking an entire 3D-IC or System-on-Chip (SoC).

Some sophisticated 2.5D assemblies even incorporate TSVs and 3D components. Several foundries now support 2.5D packaging.[7][8][9][10][11] The success of 2.5D assembly has given rise to "chiplets" – small, functional circuit blocks designed to be combined in mix-and-match fashion on interposers. Several high-end products[12][13] already take advantage of these LEGO-style chiplets; some experts predict[14] the emergence of an industry-wide chiplet ecosystem. Interposers can be larger than the reticle size which is the maximum area that can be projected by a photolithography scanner or stepper. [15]

  1. ^ "Advanced Packaging".
  2. ^ "2.5D Technology". Open-silicon.com. Archived from the original on August 5, 2020. Retrieved July 21, 2020.
  3. ^ a b Maxfield, Max (April 8, 2012). "2D vs. 2.5D vs. 3D ICs 101". EE Times.
  4. ^ Santarini, Mike (March 27, 2012). "2.5D ICs are more than a stepping stone to 3D ICs". EE Times.
  5. ^ Zhang, Xiaowu; Lin, Jong Kai; Wickramanayaka, Sunil; Zhang, Songbai; Weerasekera, Roshan; Dutta, Rahul; Chang, Ka Fai; Chui, King-Jien; Li, Hong Yu; Wee Ho, David Soon; Ding, Liang; Katti, Guruprasad; Bhattacharya, Suryanarayana; Kwong, Dim-Lee (June 1, 2015). "Heterogeneous 2.5D integration on through silicon interposer". Applied Physics Reviews. 2 (2): 021308. Bibcode:2015ApPRv...2b1308Z. doi:10.1063/1.4921463 – via NASA ADS.
  6. ^ "Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space" (PDF). Department of Electrical and Computer Engineering, UC Santa Barbara. 2016. Retrieved October 20, 2020.
  7. ^ "Intel Custom Foundry EMIB". Intel Corporation. Archived from the original on July 13, 2015.
  8. ^ "About 2.5D Technology". NHanced Semiconductors, Inc. March 23, 2017.
  9. ^ "Custom ASICs". Marvell.com.
  10. ^ Wong, William G. (June 6, 2016). "Q&A: A Deeper Look at Marvell's MoChi Technology". Electronicdesign.com.
  11. ^ "What is SoIC?". Taiwan Semiconductor Manufacturing Company Ltd.
  12. ^ "Elite Performance with AMD Ryzen 3000XT Series Processors". AMD.com. Retrieved October 20, 2020.
  13. ^ "Marvell Introduces Industry's First Hyper-Scale Quad ARM Cortex-A72 and Dual Cortex-A53 Based Chips on Marvell's Revolutionary MoChi and FLC Architecture". Marvell.com. October 6, 2015.
  14. ^ Moore, Samuel K. (April 12, 2019). "Intel's View of the Chiplet Revolution". IEEE Spectrum: Technology, Engineering, and Science News.
  15. ^ "TSMC Announces 2x Reticle CoWoS for Next-Gen 5nm HPC Applications". 3 March 2020.