2 nm process

Semiconductor
device
fabrication
MOSFET scaling
(process nodes)
Future

In semiconductor manufacturing, the 2 nm process is the next MOSFET (metal–oxide–semiconductor field-effect transistor) die shrink after the 3 nm process node.

The term "2 nanometer", or alternatively "20 angstrom" (a term used by Intel), has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by the Institute of Electrical and Electronics Engineers (IEEE), a "2.1 nm node range label" is expected to have a contacted gate pitch of 45 nanometers and a tightest metal pitch of 20 nanometers.[1]

Process Gate pitch Metal pitch Year
7 nm 60 nm 40 nm 2018
5 nm 51 nm 30 nm 2020
3 nm 48 nm 24 nm 2022
2 nm 45 nm 20 nm 2025
1 nm 42 nm 16 nm 2027

As such, 2 nm is used primarily as a marketing term by the semiconductor industry to refer to a new, improved generation of chips in terms of increased transistor density (a higher degree of miniaturization), increased speed, and reduced power consumption compared to the previous 3 nm node generation.[2][3]

TSMC began risk production of its 2 nm process in July 2024, with mass production planned for the second half of 2025,[4][5] and Samsung plans to start production in 2025.[6] Intel initially forecasted production in 2024 but scrapped its 2 nm node in favor of the smaller 18 angstrom (18A) node.[7]

  1. ^ INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS: More Moore, IEEE, 2021, p. 7, archived from the original on 7 August 2022, retrieved 7 August 2022
  2. ^ "TSMC's 7nm, 5nm, and 3nm "are just numbers… it doesn't matter what the number is"". 10 September 2019. Archived from the original on 17 June 2020. Retrieved 20 April 2020.
  3. ^ Samuel K. Moore (21 July 2020). "A Better Way to Measure Progress in Semiconductors: It's time to throw out the old Moore's Law metric". IEEE Spectrum. IEEE. Archived from the original on 2 December 2020. Retrieved 20 April 2021.
  4. ^ Cite error: The named reference tsmc_rm_2022 was invoked but never defined (see the help page).
  5. ^ Salman, Ali (9 July 2024). "Apple Supplier TSMC Will Begin Trial Production Of 2nm Chips Next Week, Aiming To Secure A Stable Yield Before Mass Production". Wccftech. Retrieved 10 September 2024.
  6. ^ Shilov, Anton. "Samsung Foundry Unveils Updated Roadmap: BSPDN and 2nm Evolution Through 2027". www.anandtech.com. Retrieved 10 September 2024.
  7. ^ Alcorn, Paul (4 September 2024). "Intel announces cancellation of 20A process node for Arrow Lake, goes with external nodes instead, likely TSMC [Updated]". Tom's Hardware. Retrieved 10 September 2024.