| General information | |
|---|---|
| Launched | 2023 |
| Designed by | ARM Ltd. |
| Cache | |
| L1 cache | 64/128 KiB (32/64 KiB I-cache with parity, 32/64 KiB D-cache) per core |
| L2 cache | 0–512 KiB per complex |
| L3 cache | 256 KiB – 32 MiB (optional) |
| Architecture and classification | |
| Microarchitecture | ARM Cortex-A520 |
| Instruction set | ARMv9.2-A |
| Products, models, variants | |
| Product code name |
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| History | |
| Predecessor | ARM Cortex-A510 |
| Successor | ARM Cortex-A530 |
The ARM Cortex-A520 is a "little" CPU core model from Arm unveiled in TCS23 (total compute solution) [1][2][3] it serves as a successor to the CPU core ARM Cortex-A510. The Cortex-A500 CPU cores series generally focus on high efficiency, the CPU core can be paired with the other CPU cores in its family like ARM Cortex-A720 or/and Cortex-X4 in a CPU cluster.[4]