ARM Cortex-X1

ARM Cortex-X1
General information
Launched	2020
Designed by	ARM Ltd.
Performance
Max. CPU clock rate	to 3.0 GHz in phones and 3.3 GHz in tablets/laptops
Address width	40-bit
Cache
L1 cache	128 KiB (64 KiB I-cache with parity, 64 KiB D-cache) per core
L2 cache	512–1024 KiB per core
L3 cache	512 KiB – 8 MiB (optional)
Architecture and classification
Microarchitecture	ARM Cortex-X1
Instruction set	ARMv8-A: A64, A32, and T32 (at the EL0 only)
Extensions	ARMv8.1-A, ARMv8.2-A, cryptography, RAS, ARMv8.3-A LDAPR instructions, ARMv8.4-A dot product;
Physical specifications
Cores	1–4 per cluster;
Products, models, variants
Product code name	Hera;
Variant	ARM Cortex-A78, ARM Neoverse V1;
History
Successor	ARM Cortex-X2

The ARM Cortex-X1 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Austin design centre as part of ARM's Cortex-X Custom (CXC) program.^[1]^[2]

^ "Introducing the Arm Cortex-X Custom program". community.arm.com. Retrieved 2020-06-18.
^ Ltd, Arm. "Cortex-X Custom CPU program". Arm | The Architecture for the Digital World. Retrieved 2020-06-18.