| General information | |
|---|---|
| Launched | 2008 |
| Discontinued | 2013 |
| Common manufacturer |
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| Performance | |
| Max. CPU clock rate | 600 MHz to 2.13 GHz |
| FSB speeds | 400 MHz to 667 MHz |
| Architecture and classification | |
| Technology node | 45 nm to 32 nm |
| Instruction set | x86-16, IA-32, x86-64 (some) |
| Instructions | MMX |
| Extensions | |
| Physical specifications | |
| Cores |
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| Package |
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| Products, models, variants | |
| Core names |
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| History | |
| Successor | Silvermont |
Bonnell is a CPU microarchitecture used by Intel Atom processors which can execute up to two instructions per cycle.[1][2] Like many other x86 microprocessors, it translates x86 instructions (CISC instructions) into simpler internal operations (sometimes referred to as micro-ops, effectively RISC style instructions) prior to execution. The majority of instructions produce one micro-op when translated, with around 4% of instructions used in typical programs producing multiple micro-ops. The number of instructions that produce more than one micro-op is significantly fewer than the P6 and NetBurst microarchitectures. In the Bonnell microarchitecture, internal micro-ops can contain both a memory load and a memory store in connection with an ALU operation, thus being more similar to the x86 level and more powerful than the micro-ops used in previous designs.[3] This enables relatively good performance with only two integer ALUs, and without any instruction reordering, speculative execution or register renaming. A side effect of having no speculative execution is invulnerability against Meltdown and Spectre.
The Bonnell microarchitecture therefore represents a partial revival of the principles used in earlier Intel designs such as P5 and the i486, with the sole purpose of enhancing the performance per watt ratio. However, Hyper-Threading is implemented in an easy (i.e. low-power) way to employ the whole pipeline efficiently by avoiding the typical single thread dependencies.[3]