Coherent Accelerator Processor Interface

Coherent Accelerator Processor Interface
Year created2014; 10 years ago (2014)
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Coherent Accelerator Processor Interface (CAPI), is a high-speed processor expansion bus standard for use in large data center computers, initially designed to be layered on top of PCI Express, for directly connecting central processing units (CPUs) to external accelerators like graphics processing units (GPUs), ASICs, FPGAs or fast storage.[1][2] It offers low latency, high speed, direct memory access connectivity between devices of different instruction set architectures.

  1. ^ Agam Shah (17 December 2014). "IBM's new Power8 doubles performance of Watson chip". PC World. Archived from the original on 1 February 2018. Retrieved 17 December 2014.
  2. ^ "IBM Power8 Processor Detailed - Features 22nm Design With 12 Cores, 96 MB eDRAM L3 Cache and 4 GHz Clock Speed". WCCFtech. 27 August 2013. Retrieved 17 December 2014.