Domino logic

For logic gates built from dominoes, see Domino computer.
General domino logic implementation, with the pull-down network symbolising a network of NMOS transistors.[1]

Domino logic is a CMOS-based evolution of dynamic logic techniques consisting of a dynamic logic gate cascaded into a static CMOS inverter.[2] The term derives from the fact that in domino logic, each stage ripples the next stage for evaluation, similar to dominoes falling one after the other. Domino logic contrasts with other solutions to the cascade problem where cascading is interrupted by clocks or other means.

Domino logic was developed to speed up circuits, solving the premature cascade problem, typically by inserting static CMOS inverters between domino stages to avoid premature discharge of further cascaded dynamic logic gates.[3] Domino logic allows a rail-to-rail logic swing, with the output being able to switch from the power supply voltage to the ground voltage.

  1. ^ Sharma, Ankita; Rao, Divyanshu; Mohan, Ravi (December 2016). "Design and Implementation of Domino Logic Circuit in CMOS" (PDF). Journal of Network Communications and Emerging Technologies. 6 (12): 14–17.
  2. ^ Srivastava, P.; Pua, A.; Welch, L. (1998). "Issues in the design of domino logic circuits". Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222). IEEE Comput. Soc. pp. 108–112. doi:10.1109/GLSV.1998.665208. ISBN 978-0-8186-8409-8. S2CID 45670900.
  3. ^ Natarajan, Suriyaprakash; Gupta, Sandeep K.; Breuer, Melvin A. (2001). Proceedings International Test Conference 2001 (Cat. No.01CH37260). Vol. 13. IEEE. pp. 367–376. doi:10.1109/test.2001.966628. ISBN 0-7803-7169-0.