Front end of line

Illustration of FEOL (device generation in the silicon, bottom) and BEOL (depositing metalization layers, middle part) to connect the devices.
CMOS fabrication process

The front end of line (FEOL) is the first portion of IC fabrication where the individual components (transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate.[1] FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers.[2]

  1. ^ Karen A. Reinhardt and Werner Kern (2008). Handbook of Silicon Wafer Cleaning Technology (2nd ed.). William Andrew. p. 202. ISBN 978-0-8155-1554-8.
  2. ^ "FEOL (Front End of Line: substrate process, the first half of wafer processing) 1. Isolation | USJC：United Semiconductor Japan Co., Ltd". USJC：United Semiconductor Japan Co., Ltd. | 三重県桑名市の300mm半導体ウェーハ工場を製造拠点にしたファウンドリ専業メーカーです。超低消費電力、不揮発メモリなど先進テクノロジーを世界中のお客様に提供しています。 (in Japanese). 2019-02-22. Retrieved 2022-09-27.