| Designer | HP and Intel |
|---|---|
| Bits | 64-bit |
| Introduced | 2001 |
| Design | EPIC |
| Type | Load–store |
| Encoding | Fixed |
| Branching | Condition register |
| Endianness | Selectable |
| Registers | |
| General-purpose | 128 (64 bits plus 1 trap bit; 32 are static, 96 use register windows); 64 1-bit predicate registers |
| Floating point | 128 |
IA-64 (Intel Itanium architecture) is the instruction set architecture (ISA) of the discontinued Itanium family of 64-bit Intel microprocessors. The basic ISA specification originated at Hewlett-Packard (HP), and was subsequently implemented by Intel in collaboration with HP. The first Itanium processor, codenamed Merced, was released in 2001.
The Itanium architecture is based on explicit instruction-level parallelism, in which the compiler decides which instructions to execute in parallel. This contrasts with superscalar architectures, which depend on the processor to manage instruction dependencies at runtime. In all Itanium models, up to and including Tukwila, cores execute up to six instructions per cycle.
In 2008, Itanium was the fourth-most deployed microprocessor architecture for enterprise-class systems, behind x86-64, Power ISA, and SPARC.[1]
In 2019, Intel announced the discontinuation of the last of the CPUs supporting the IA-64 architecture.