Latch-up

In electronics, a latch-up is a type of short circuit which can occur in an integrated circuit (IC). More specifically, it is the inadvertent creation of a low-impedance path between the power supply rails of a MOSFET circuit, triggering a parasitic structure which disrupts proper functioning of the part, possibly even leading to its destruction due to overcurrent. A power cycle is required to correct this situation.

The parasitic structure is usually equivalent to a thyristor (or SCR), a PNPN structure which acts as a PNP and an NPN transistor stacked next to each other. During a latch-up when one of the transistors is conducting, the other one begins conducting too. They both keep each other in saturation for as long as the structure is forward-biased and some current flows through it - which usually means until a power-down. The SCR parasitic structure is formed as a part of the totem-pole PMOS and NMOS transistor pair on the output drivers of the gates.

The latch-up does not have to happen between the power rails - it can happen at any place where the required parasitic structure exists. A common cause of latch-up is a positive or negative voltage spike on an input or output pin of a digital chip that exceeds the rail voltage by more than a diode drop. Another cause is the supply voltage exceeding the absolute maximum rating, often from a transient spike in the power supply. It leads to a breakdown of an internal junction. This frequently happens in circuits which use multiple supply voltages that do not come up in the required sequence on power-up, leading to voltages on data lines exceeding the input rating of parts that have not yet reached a nominal supply voltage. Latch-ups can also be caused by an electrostatic discharge event.

Intrinsic bipolar junction transistors in the CMOS technology

Another common cause of latch-ups is ionizing radiation which makes this a significant issue in electronic products designed for space (or very high-altitude) applications. A single event latch-up is a latch-up caused by a single event upset, typically heavy ions or protons from cosmic rays or solar flares.[1][2] Single-event latchup (SEL) can be completely eliminated by several manufacturing techniques, as part of radiation hardening.[3]

High-power microwave interference can also trigger latch ups.[4]

Both CMOS integrated circuits and TTL integrated circuits are more susceptible to latch-up at higher temperatures.[5]

  1. ^ R. Koga, K.B. Crawford, S.J. Hansel, B.M. Johnson, D.D. Lau, S.H. Penzin, S.D. Pinkerton, M.C. Maher. "AN-932 SEU and Latch Up Tolerant Advanced CMOS Technology". 1994.
  2. ^ "Single-event latch-up protection of integrated circuits". 2002.
  3. ^ D. J. Shirley and M. K. McLelland. "The Next-Generation SC-7 RISC Spaceflight Computer". Southwest Research Institute. p. 3
  4. ^ H. Wang, J. Li, H. Li, K. Xiao and H. Chen. "Experimental study and Spice simulation of CMOS inverters latch-up effects due to high power microwave interference". 2008.
  5. ^ Cooper, M.S.; Retzler, J.P. "High Temperature Schottky TTL latch-up". doi: 10.1109/TNS.1978.4329568 1978.