Ling adder

In electronics, a Ling adder is a particularly fast binary adder designed using H. Ling's equations and generally implemented in BiCMOS. Samuel Naffziger of Hewlett-Packard presented an innovative 64 bit adder in 0.5 μm CMOS based on Ling's equations at ISSCC 1996. The Naffziger adder's delay was less than 1 nanosecond, or 7 FO4.[1]

  1. ^ Naffziger, S. (8–10 February 1996). "A Sub-Nanosecond 0.5um 64b Adder Design" (PDF). Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference. San Francisco. pp. 362–363. Archived from the original (PDF) on 10 April 2006.