 | This article needs additional citations for verification. (December 2006) |
| Low Pin Count | |
| Year created | 1998 |
|---|---|
| Created by | Intel |
| Supersedes | Industry Standard Architecture |
| Superseded by | Enhanced Serial Peripheral Interface Bus (2016) |
| Width in bits | 4 |
| Speed | 33 MHz |
| Style | Parallel |
| Hotplugging interface | no |
| External interface | no |
The Low Pin Count (LPC) bus is a computer bus used on IBM-compatible personal computers to connect low-bandwidth devices to the CPU, such as the BIOS ROM (BIOS ROM was moved to the Serial Peripheral Interface (SPI) bus in 2006[1]), "legacy" I/O devices (integrated into Super I/O, Embedded Controller, CPLD, and/or IPMI chip), and Trusted Platform Module (TPM).[2] "Legacy" I/O devices usually include serial and parallel ports, PS/2 keyboard, PS/2 mouse, and floppy disk controller.
Most PC motherboards with an LPC bus have either a Platform Controller Hub (PCH) or a southbridge chip, which acts as the host and controls the LPC bus. All other devices connected to the physical wires of the LPC bus are peripherals.
- ^ Kovah, Xeno; Kallenberg, Corey; LegbaCore LLC (15 October 2015). SPI Flash (PDF). Advanced x86: BIOS and system management mode internals. OpenSecurityTraining.info. p. 5.
- ^ Johannes Winter (2011). "A Hijacker's Guide to the LPC bus". tugraz.at. Retrieved 2013-12-19.