Metastability (electronics)

Figure 1. An illustration of metastability in a synchronizer, where data crosses between clock domains. In the worst case, depending on timing, the metastable condition at Ds can propagate to Dout and through the following logic into more of the system, causing undefined and inconsistent behavior.

In electronics, metastability is the ability of a digital electronic system to persist for an unbounded time in an unstable equilibrium or metastable state.[1] In digital logic circuits, a digital signal is required to be within certain voltage or current limits to represent a '0' or '1' logic level for correct circuit operation; if the signal is within a forbidden intermediate range it may cause faulty behavior in logic gates the signal is applied to. In metastable states, the circuit may be unable to settle into a stable '0' or '1' logic level within the time required for proper circuit operation. As a result, the circuit can act in unpredictable ways, and may lead to a system failure, sometimes referred to as a "glitch".[2] Metastability is an instance of the Buridan's ass paradox.

Metastable states are inherent features of asynchronous digital systems, and of systems with more than one independent clock domain. In self-timed asynchronous systems, arbiters are designed to allow the system to proceed only after the metastability has resolved, so the metastability is a normal condition, not an error condition.[3] In synchronous systems with asynchronous inputs, synchronizers are designed to make the probability of a synchronization failure acceptably small.[4] Metastable states are avoidable in fully synchronous systems when the input setup and hold time requirements on flip-flops are satisfied.

  1. ^ Thomas J. Chaney and Charles E. Molnar (April 1973). "Anomalous Behavior of Synchronizer and Arbiter Circuits" (PDF). IEEE Transactions on Computers. C-22 (4): 421–422. doi:10.1109/T-C.1973.223730. ISSN 0018-9340. S2CID 12594672.
  2. ^ Chaney, Thomas J. "My Work on All Things Metastable OR Me and My Glitch" (PDF). Archived from the original (PDF) on 2015-12-08. Retrieved 2015-11-05.
  3. ^ John Bainbridge (2002). Asynchronous system-on-chip interconnect. Springer. p. 18. ISBN 978-1-85233-598-4.
  4. ^ Chaney, Thomas J. ""Reprint of Technical Memorandum No. 10, "The Glitch Phenomenon" (1966)"".Washington University in St. Louis