Program counter

Front panel of an IBM 701 computer introduced in 1952. Lights in the middle display the contents of various registers. The instruction counter is at the lower left.

The program counter (PC),[1] commonly called the instruction pointer (IP) in Intel x86 and Itanium microprocessors, and sometimes called the instruction address register (IAR),[2][1] the instruction counter,[3] or just part of the instruction sequencer,[4] is a processor register that indicates where a computer is in its program sequence.[5][nb 1]

Usually, the PC is incremented after fetching an instruction, and holds the memory address of ("points to") the next instruction that would be executed.[6][nb 2]

Processors usually fetch instructions sequentially from memory, but control transfer instructions change the sequence by placing a new value in the PC. These include branches (sometimes called jumps), subroutine calls, and returns. A transfer that is conditional on the truth of some assertion lets the computer follow a different sequence under different conditions.

A branch provides that the next instruction is fetched from elsewhere in memory. A subroutine call not only branches but saves the preceding contents of the PC somewhere. A return retrieves the saved contents of the PC and places it back in the PC, resuming sequential execution with the instruction following the subroutine call.

  1. ^ a b Hayes, John P. (1978). Computer Architecture and Organization. McGraw-Hill. p. 245. ISBN 0-07-027363-4.
  2. ^ Cite error: The named reference Mead_1980 was invoked but never defined (see the help page).
  3. ^ Cite error: The named reference IBM_1953 was invoked but never defined (see the help page).
  4. ^ Cite error: The named reference Katzan_1971 was invoked but never defined (see the help page).
  5. ^ Bates, Martin (2011). "Microcontroller Operation". PIC Microcontrollers. Elsevier. p. 27–44. doi:10.1016/b978-0-08-096911-4.10002-3. ISBN 978-0-08-096911-4. Program Counter (PC) is a register that keeps track of the program sequence, by storing the address of the instruction currently being executed. It is automatically loaded with zero when the chip is powered up or reset. As each instruction is executed, PC is incremented (increased by one) to point to the next instruction.
  6. ^ Cite error: The named reference Silberschatz_2018 was invoked but never defined (see the help page).
  7. ^ Cite error: The named reference ARM_AG12 was invoked but never defined (see the help page).


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