Quilt packaging

Quilt Packaging “nodules” extend out from the edge of microchips.
Quilt Packaging Nodules have solder on top to enable chip to chip interconnection
3x3 Chip Array Using Quilt Packaging Interconnect Technology
QP Chiplets can be quilted together in most any orientation.

Quilt Packaging (QP) is an integrated circuit packaging and chip-to-chip interconnect packaging technology that utilizes “nodule” structures that extend out horizontally from the edges of microchips to make chip-to-chip interconnections.[1][2] 

QP nodules are created as an integral part of a microchip using standard back end of the line techniques in semiconductor device fabrication. Solder is then electroplated on top of the nodules to enable the chip to chip interconnection with sub-micron alignment accuracy.[3]

Small high yielding “chiplets” made from any semiconductor material (silicon, gallium arsenide, silicon carbide, gallium nitride, etc.), can be “quilted” together to create larger multi-function meta-chip.[4]  Thus, QP technology can integrate multiple chips with dissimilar technologies or substrate materials in planar, 2.5D and 3D configurations.[5]

  1. ^ Zheng, Quanling; Kopp, David; Khan, Mohammad Ashraf; Fay, Patrick; Kriman, Alfred M.; Bernstein, Gary H. (March 2014). "Investigation of Quilt Packaging Interchip Interconnect With Solder Paste". IEEE Transactions on Components, Packaging and Manufacturing Technology. 4 (3): 400–407. doi:10.1109/tcpmt.2014.2301738. ISSN 2156-3950. S2CID 36676516.
  2. ^ Ashraf Khan, M.; Zheng, Quanling; Kopp, David; Buckhanan, Wayne; Kulick, Jason M.; Fay, Patrick; Kriman, Alfred M.; Bernstein, Gary H. (2015-06-01). "Thermal Cycling Study of Quilt Packaging". Journal of Electronic Packaging. 137 (2). doi:10.1115/1.4029245. ISSN 1043-7398.
  3. ^ Ahmed, Tahsin; Butler, Thomas; Khan, Aamir A.; Kulick, Jason M.; Bernstein, Gary H.; Hoffman, Anthony J.; Howard, Scott S. (2013-09-10). Sasián, José; Youngworth, Richard N. (eds.). "FDTD modeling of chip-to-chip waveguide coupling via optical quilt packaging". Optical System Alignment, Tolerancing, and Verification VII. 8844. SPIE: 88440C. Bibcode:2013SPIE.8844E..0CA. doi:10.1117/12.2024088. S2CID 120463545.
  4. ^ Khan, M. Ashraf; Kulick, Jason M.; Kriman, Alfred M.; Bernstein, Gary H. (January 2012). "Design and Robustness of Quilt Packaging Superconnect". International Symposium on Microelectronics. 2012 (1): 000524–000530. doi:10.4071/isom-2012-poster_khan. ISSN 2380-4505.
  5. ^ Sparkman, Kevin; LaVeigne, Joe; McHugh, Steve; Kulick, Jason; Lannon, John; Goodwin, Scott (2014-05-29). Holst, Gerald C.; Krapels, Keith A.; Ballard, Gary H.; Buford, James A.; Murrer, R. Lee (eds.). "Scalable emitter array development for infrared scene projector systems". Infrared Imaging Systems: Design, Analysis, Modeling, and Testing XXV. 9071. SPIE: 90711I. Bibcode:2014SPIE.9071E..1IS. doi:10.1117/12.2054360. S2CID 53508849.