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![]() RapidIO - the unified fabric for Performance Critical Computing | |
Year created | 2000 |
---|---|
Width in bits | Port widths of 1, 2, 4, 8, and 16 lanes |
No. of devices | Sizes of 256, 65,536, and 4,294,967,296 |
Speed | Per lane (each direction):
|
Style | Serial |
Hotplugging interface | Yes |
External interface | Yes, Chip-Chip, Board-Board (Backplane), Chassis-Chassis |
Website | www |
The RapidIO architecture is a high-performance packet-switched electrical connection technology. It supports messaging, read/write and cache coherency semantics. Based on industry-standard electrical specifications such as those for Ethernet, RapidIO can be used as a chip-to-chip, board-to-board, and chassis-to-chassis interconnect.