This is a documentation subpage for Template:Infobox CPU. It may contain usage information, categories and other content that is not part of the original template page. |
This template uses Lua: |
This template is for CPUs, SoCs and SiPs. For generic hardware components, see Template:Infobox computer hardware.
This article is missing information about one good example of this infobox would be nice here. But as long as three architecture-parameters and the four name-parameters are not clearly defined it is difficult. (October 2019) |
[[File:{{{image}}}|{{{image_size}}}|alt={{{alt}}}]] | |
Launching | {{{launching}}} |
---|---|
Launched | {{{produced-start}}} |
Discontinued | {{{produced-end}}} |
Marketed by | {{{soldby}}} |
Designed by | {{{designfirm}}} |
Common manufacturers |
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CPUID code | {{{cpuid}}} |
Product code | {{{code}}} |
Max. CPU clock rate | {{{slowest}}} {{{slow-unit}}} to {{{fastest}}} {{{fast-unit}}} |
FSB speeds | {{{fsb-slowest}}} {{{fsb-slow-unit}}} to {{{fsb-fastest}}} {{{fsb-fast-unit}}} |
HyperTransport speeds | {{{hypertransport-slowest}}} {{{hypertransport-slow-unit}}} to {{{hypertransport-fastest}}} {{{hypertransport-fast-unit}}} |
QPI speeds | {{{qpi-slowest}}} {{{qpi-slow-unit}}} to {{{qpi-fastest}}} {{{qpi-fast-unit}}} |
DMI speeds | {{{dmi-slowest}}} {{{dmi-slow-unit}}} to {{{dmi-fastest}}} {{{dmi-fast-unit}}} |
Data width | {{{data-width}}} |
Address width | {{{address-width}}} |
Virtual address width | {{{virtual-width}}} |
L1 cache | {{{l1cache}}} |
L2 cache | {{{l2cache}}} |
L3 cache | {{{l3cache}}} |
L4 cache | {{{l4cache}}} |
Last level cache | {{{llcache}}} |
Application | {{{application}}} |
Technology node | {{{size-from}}} to {{{size-to}}} |
Microarchitecture | {{{microarch}}} |
Instruction set | {{{arch}}} |
Instructions | {{{instructions}}} |
Extensions |
|
Number of instructions | {{{numinstructions}}} |
Transistors |
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Cores |
|
Memory (RAM) |
|
GPU | {{{gpu}}} |
Co-processor | {{{co-processor}}} |
Packages |
|
Sockets |
|
Core names |
|
Product code names |
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Models |
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Brand names |
|
Variant |
|
Predecessor | {{{predecessor}}} |
Successor | {{{successor}}} |
{{{support status}}} |
{{Infobox CPU
| name =
| hide_subheadings =
| image =
| image_size =
| alt =
| caption =
<!----------------- General Info ----------------->
| launching =
| produced-start =
| produced-end =
| soldby =
| designfirm =
| manuf1 = <!-- manuf1..10 -->
| cpuid =
| code =
<!----------------- Performance ------------------>
| slowest =
| fastest =
| slow-unit =
| fast-unit =
| fsb-slowest =
| fsb-fastest =
| fsb-slow-unit =
| fsb-fast-unit =
| hypertransport-slowest =
| hypertransport-fastest =
| hypertransport-slow-unit =
| hypertransport-fast-unit =
| qpi-slowest =
| qpi-fastest =
| qpi-slow-unit =
| qpi-fast-unit =
| dmi-slowest =
| dmi-fastest =
| dmi-slow-unit =
| dmi-fast-unit =
| data-width =
| address-width =
| virtual-width =
<!-------------------- Cache --------------------->
| l1cache =
| l2cache =
| l3cache =
| l4cache =
| llcache =
<!------- Architecture and classification -------->
| application =
| size-from =
| size-to =
| microarch =
| arch =
| instructions =
| extensions =
| numinstructions =
<!----------- Physical specifications ------------>
| transistors =
| numcores =
| amountmemory =
| gpu =
| co-processor =
| pack1 = <!-- pack1..9 -->
| sock1 = <!-- sock1..9 -->
<!--------- Products, models, variants ----------->
| core1 = <!-- core1..9 -->
| pcode1 = <!-- pcode1..9 -->
| model1 = <!-- model1..9 -->
| brand1 = <!-- brand1..9 -->
| variant =
<!------------------ History ------------------->
| predecessor =
| successor =
<!------------------ Support status ------------------->
| support status =
}}