Template:Infobox CPU architecture

SPARC
Designer	Sun Microsystems
Bits	64-bit (32 → 64)
Introduced	1985
Version	V9 (1993)
Design	RISC
Type	Register-Register
Encoding	Fixed
Branching	Condition code
Endianness	Bi (Big → Bi)
Page size	8 KiB
Extensions	VIS 1.0, 2.0, 3.0
Open	Yes
Registers
General-purpose	31 (G0 = 0; non-global registers use register windows)
Floating point	32

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This template uses Lua:

This template is for CPU instruction set architectures.

Usage

{{Infobox CPU architecture
| name        = 
| image       = 
| image_size  = 
| alt         = 
| caption     = 
| designer    = 
| bits        = 
| introduced  = 
| version     = 
| design      = 
| type        = 
| encoding    = 
| branching   = 
| endianness  = 
| page size   = 
| extensions  = 
| open        = 
| predecessor = 
| successor   = 
| registers   = 
| gpr         = 
| fpr         = 
| vpr         = 
}}

Description

{{Infobox CPU architecture
| name        = Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM
| designer    = Designer of the architecture
| bits        = Width of accumulator/general registers/stack top, e.g. 32-bit, 64-bit
| introduced  = Year introduced
| version     = Version/revision of architecture/ISA
| design      = Design strategy, e.g. RISC, CISC
| type        = Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory
| encoding    = Instruction set encoding, e.g. Fixed or Variable
| branching   = Branching evaluation, e.g. Condition register, Condition code, Compare and branch
| endianness  = Byte ordering, i.e. Little, Big, Bi
| page size   = Primary size of page, i.e. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions
| extensions  = ISA extensions, i.e. MMX, SSE, AltiVec, etc
| predecessor = Earlier architecture(s) this one is based on, if it has a separate page
| successor   = Later architecture(s) based primarily on this one, if it has a separate page
| open        = Is the architecture open or not? (as in free or proprietary)
| registers   = Number and size of processor registers 
| gpr         = Number of general-purpose registers (and size, if not indicated by bits=)
| fpr         = Number of floating-point registers (and size, if not indicated by bits=)
| vpr         = Number of vector registers (and size, if not indicated by bits=)
}}

All fields are optional.

Example

{{Infobox CPU architecture
| name       = SPARC
| designer   = [[Sun Microsystems]]
| bits       = 64-bit (32 → 64)
| introduced = 1985
| version    = V9 (1993)
| design     = RISC
| type       = Register-Register
| encoding   = Fixed
| branching  = Condition code
| endianness = Bi (Big → Bi)
| page size  = 8 KiB
| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0
| open       = Yes
| gpr        = 31 (G0 = 0; non-global registers use [[register window]]s)
| fpr        = 32
}}

Parameters

All parameters are optional.

name: Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM
designer: Designer of the architecture
bits: Width of accumulator/general registers/stack top, e.g. 32-bit, 64-bit
introduced: Year introduced
version: Version/revision of architecture/ISA
design: Design strategy, e.g. RISC, CISC
type: Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory
encoding: Instruction set encoding, e.g. Fixed or Variable
branching: Branching evaluation, e.g. Condition register, Condition code, Compare and branch
endianness: Byte ordering, e.g. Little, Big, Bi
page size: Primary size of page, e.g. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions
extensions: ISA extensions, e.g. MMX, SSE, AltiVec
open: Is the architecture open or not? (as in free or proprietary)
predecessor: Earlier architecture(s) this one is based on, if it has a separate page
successor: Later architecture(s) based primarily on this one, if it has a separate page

registers: Number and size of processor registers
gpr: Number of general-purpose registers (and size, if not indicated by bits=)
fpr: Number of floating-point registers (and size, if not indicated by bits=)
vpr: Number of vector registers (and size, if not indicated by bits=)

Template:Infobox CPU architecture

Usage

Description

Example

Parameters

See also