Three-dimensional integrated circuit

A three-dimensional integrated circuit (3D IC) is a MOS (metal-oxide semiconductor) integrated circuit (IC) manufactured by stacking as many as 16 or more ICs and interconnecting them vertically using, for instance, through-silicon vias (TSVs) or Cu-Cu connections,[1][2] so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional processes. The 3D IC is one of several 3D integration schemes that exploit the z-direction to achieve electrical performance benefits in microelectronics and nanoelectronics.

3D integrated circuits can be classified by their level of interconnect hierarchy at the global (package), intermediate (bond pad) and local (transistor) level.[3] In general, 3D integration is a broad term that includes such technologies as 3D wafer-level packaging (3DWLP); 2.5D and 3D interposer-based integration; 3D stacked ICs (3D-SICs); 3D heterogeneous integration; and 3D systems integration;[4][5] as well as true monolithic 3D ICs.

International organizations such as the Jisso Technology Roadmap Committee (JIC) and the International Technology Roadmap for Semiconductors (ITRS) have worked to classify the various 3D integration technologies to further the establishment of standards and roadmaps of 3D integration.[6] As of the 2010s, 3D ICs are widely used for NAND flash memory and in mobile devices.

  1. ^ Hu, Y.H.; Liu, C.S.; Lii, M.J.; Rebibis, K. J.; Jourdain, A.; La Manna, A.; Beyne, E.; Yu, C.H. (2012). "Cu-Cu hybrid bonding as option for 3D IC stacking". 2012 IEEE International Interconnect Technology Conference. pp. 1–3. doi:10.1109/IITC.2012.6251571. ISBN 978-1-4673-1137-3.
  2. ^ Wafer Bonding: Applications and Technology. Springer. 9 March 2013. ISBN 978-3-662-10827-7.
  3. ^ "SEMI.ORG" (PDF). Archived (PDF) from the original on 2015-09-24.
  4. ^ "What is 3D Integration? - 3D InCites". Archived from the original on 2014-12-30.
  5. ^ Cite error: The named reference AutoRE-24 was invoked but never defined (see the help page).
  6. ^ "INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2011 EDITION" (PDF). Archived from the original (PDF) on 2014-12-30. Retrieved 2014-12-30.