 | This article may be too technical for most readers to understand. (September 2010) |
&sq=Qlik&lang=&file=File:Core_duo_u2500_sl9jq.png) Core Duo U2500 in BGA packaging | |
| General information | |
|---|---|
| Launched | 2006 |
| Discontinued | 2008 |
| Marketed by | Intel |
| Designed by | Intel |
| Common manufacturer |
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| CPUID code | 06Ex |
| Product code |
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| Performance | |
| Max. CPU clock rate | 1.06 GHz to 2.33 GHz |
| FSB speeds | 533 MT/s to 667 MT/s |
| Cache | |
| L1 cache | 32 KB instruction, 32 KB data per core |
| L2 cache | 2 MB, shared |
| Architecture and classification | |
| Application | Mobile |
| Technology node | 65 nm |
| Microarchitecture | P6 |
| Instruction set | x86-16, IA-32 |
| Extensions | |
| Physical specifications | |
| Cores |
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| Packages |
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| Socket | |
| Products, models, variants | |
| Brand names |
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| History | |
| Predecessor | Dothan |
| Successor | Merom |
| Support status | |
| Unsupported | |
Yonah is the code name of Intel's first generation 65 nm process CPU cores, based on cores of the earlier Banias (130 nm) / Dothan (90 nm) Pentium M microarchitecture. Yonah CPU cores were used within Intel's Core Solo and Core Duo mobile microprocessor products. SIMD performance on Yonah improved through the addition of SSE3 instructions and improvements to SSE and SSE2 implementations; integer performance decreased slightly due to higher latency cache. Additionally, Yonah included support for the NX bit.